MRF49XA Datasheet, PDF (51/102 Pages) Microchip Technology – ISM Band Sub-GHz RF Transceiver

MRF49XA
3.7 Automatic Frequency Control
The AFC block operates in two modes and these
modes depend on the strobe signals which are gov-
erned by the MFCS bit (AFCCREG<3>). The two
operating modes are as follows:
• Manual Mode
• Automatic Mode
Manual Mode: In this mode, the microcontroller pro-
vides the manual frequency control strobe signal. See
Register 2-3 (AFCCREG) for more details. One
measurement cycle can compensate for around 50-60%
of the actual frequency offset. Two measurement cycles
can compensate for 80% and three measurement cycles
can compensate for 92% of the actual frequency offset.
The AFCCT bit (STSREG<5>) is used to determine
when the actual measurement cycle has been
completed.
Automatic Mode: In this mode, the strobe signal from
the microcontroller is not required to update the Fre-
quency Offset register block, as shown in Figure 3-6.
The AFC circuit is automatically enabled when the DIO
indicates the potential incoming signal during the entire
measurement cycle and measures the same result in
two subsequent cycles. Without AFC, the transmitter
and the receiver need to be tuned precisely to the same
frequency. The RX/TX frequency offset can lower the
range. The units must be adjusted carefully during the
production. To avoid drift, a stable and efficient crystal
must be used or the output power needs to be
increased to compensate for yield loss.
The AFC block calculates the TX/RX offset using the
OFFSB bits (STSREG<3:0>). This value is used to pull
the RX synthesizer close to the transmitter frequency.
The benefits of the Automatic Frequency Control
feature are:
• Low-cost crystal can be used
• Temperature or aging drift will not cause range
loss
• Production alignment is not needed
Figure 3-6 depicts the AFC circuit for frequency offset
correction.
The Automatic Mode Selection bits, AUTOMS<1:0>
(AFCCREG<7:6>), select the type of operation (auto-
matic or manual) for performing the AFC based on the
status of the MFCS bit (AFCCREG<3>). There are four
types of operation modes for controlling the frequency:
1. (AUTOMS1 = 0, AUTOMS0 = 0): Automatic
operation of AFC is off. The MFCS bit is
controlled by the microcontroller.
2. (AUTOMS1 = 0, AUTOMS0 = 1): The circuit
measures the frequency offset only once after
power-up. Hence, extended TX to RX distance
can be achieved. In the actual application, when
the user applies a battery, the circuit measures
and compensates for the frequency offset
caused by the crystal tolerances. This method
allows the use of a low-cost quartz crystal in the
application and provides protection against
interference.
3. (AUTOMS1 = 1, AUTOMS0 = 0): The frequency
offset is automatically calculated and the center
frequency is corrected when the DIO is high.
When DIO goes low, the calculated value is
dropped.
The two methods recommended for improving the
accuracy of the AFC calculation are as follows:
• The transmit package should start with a low
effective baud rate pattern (i.e., 00110011b) as it
is easier to receive. The circuit automatically
measures the frequency offset during this initial
pattern and changes the receiving frequency
accordingly. The remaining part of the package
will be received by the corrected frequency
settings.
• The transmitter sends the first part of the packet
with a higher deviation step than required during
normal operation to help reception. After the
frequency shift correction, the deviation can be
reduced.
In both methods, when the DIO indicates poor receiving
conditions (i.e., when DIO goes low), the output register
is automatically cleared. This mode (Drop Offset mode)
is used when the receiver communicates with more than
one transmitter.
4. (AUTOMS1 = 1, AUTOMS0 = 1): This mode
(Keep Offset mode) is similar to Drop Offset
mode, but is recommended for use when the
receiver communicates with only one transmit-
ter. After a complete measuring cycle, the
measured value is kept independent of the state
of the DIO signal. In this mode, the DRSSI limit
should be carefully selected to minimize the
range hysteresis.
The AFC Offset Value (OFFSB<3:0> bits in the status
word) is represented as a two’s complement number.
The actual frequency offset is calculated as the AFC
offset value multiplied by the current PLL frequency
step (see Register 2-6 for more details).
The actual RX/TX offset can be monitored by using the
AFC status report (i.e., AFCCT bit) included in the status
word of the receiver. By reading out the status word, the
actual measured offset frequency can be derived. To get
accurate values, the AFC has to be disabled during read
by clearing the FOFEN bit (AFCCREG<0>).
The registers associated with AFC are:
• STSREG (see Register 2-1)
• AFCCREG (see Register 2-3)
• CFSREG (see Register 2-6)
• RXCREG (see Register 2-7)
• PLLCREG (see Register 2-17)
© 2009 Microchip Technology Inc.
Preliminary
DS70590B-page 49