MRF49XA Datasheet, PDF (11/102 Pages) Microchip Technology – ISM Band Sub-GHz RF Transceiver

MRF49XA
TABLE 2-1: PIN DESCRIPTION
Pin
Symbol
Type
Description
1
SDI
Digital Input
Serial data input interface to MRF49XA (SPI input signal).
2
SCK
Digital Input
Serial clock interface (SPI clock).
3
CS
Digital Input
Serial interface chip select (SPI chip/device select).
4
SDO
Digital Output Serial data output interface from MRF49XA (SPI output
signal).
5
IRO
Digital Output Interrupt Request Output: Receiver generates an
active-low interrupt request for the microcontroller on the
following events:
• The TXBREG (see Table 2-4) is ready to receive the
next byte.
• The RXFIFOREG (see Table 2-4) has received the
preprogrammed amount of bits.
• RXFIFOREG overflow/TXBREG underrun.
• Negative pulse on interrupt input pin (INT).
• Wake-up timer time-out.
• Supply voltage below the preprogrammed value is
detected.
• Power-on Reset (POR).
6
FSK/DATA/FSEL Digital Input/Output Frequency Shift Keying: Transmit FSK data input (with
internal pull-up resistor of 133 kΩ).
Data: When configured as DATA, this pin functions as
follows:
• Data In: Manually modulates the data from the external
host microcontroller when the internal TXBREG is dis-
abled. If the TXBREG is enabled, this pin can be tied
“high” or left unconnected. When reading the internal
RXFIFOREG, this pin must be pulled “low”.
• Data Out: Receives data in conjunction with RCLKOUT
when the internal FIFO is not used.
FIFO Select: Selects the FIFO and the first bit appears on
the next clock when reading the RXFIFOREG. The FSEL pin
has an internal pull-up resistor. This pin must be “high” when
the TX register is enabled. In order to achieve minimum
current consumption, keep this pin “high” in Sleep mode.
7
RCLKOUT/FCAP/ Digital Input/Output Recovery Clock Output: Provides the clock recovered from
FINT
the incoming data if:
• FTYPE bit of BBFCREG (see Table 2-5) is configured as
digital filter and
• FIFO is disabled by configuring FIFOEN bit of
GENCREG (see Table 2-5)
Filter Capacitor: This pin is a raw baseband data if the
FTYPE bit of BBFCREG is configured as a configuration
filter. The pin can be used by the host microcontroller for data
recovery.
FIFO Interrupt: When the internal FIFO, FIFOEN bit of
GENCREG is enabled, this pin acts as a FIFO full interrupt,
indicating that the FIFO has been filled to its preprogrammed
limit (see FFBC<3:0> bits in FIFORSTREG in Table 2-5).
8
CLKOUT
Digital Output Clock Output: The transceiver’s clock output can be used by
the host microcontroller as a clock source.
© 2009 Microchip Technology Inc.
Preliminary
DS70590B-page 9