MRF49XA Datasheet, PDF (24/102 Pages) Microchip Technology – ISM Band Sub-GHz RF Transceiver

MRF49XA
REGISTER 2-3: AFCCREG: AUTOMATIC FREQUENCY CONTROL CONFIGURATION REGISTER
(POR: 0xC4F7) (CONTINUED)
bit 0
FOFEN: Frequency Offset Enable bit
1 = Enables the frequency offset calculation using the AFC circuit
0 = Disables the frequency offset calculation using the AFC circuit
Note 1:
2:
3:
The FRES is the frequency tuning resolution for each band. The FRES for each band is as follows:
433 MHz = 2.5 kHz
868 MHz = 5 kHz
915 MHz = 7.5 kHz
The offset error value is stored in the Offset register (FOREN bit should be enabled) in the AFC block and
is added to the frequency control word of the PLL. Reset this bit before initiating another sample.
In High-Accuracy (Fine) mode, the processing time is twice the regular mode, but the uncertainty of the
measurement is significantly reduced.
DS70590B-page 22
Preliminary
© 2009 Microchip Technology Inc.