MRF49XA Datasheet, PDF (55/102 Pages) Microchip Technology – ISM Band Sub-GHz RF Transceiver

MRF49XA
3.9.2.3 TXOWRXOF
1. Transmit mode
In this mode, the TXOWRXOF and TXRXFIFO
bits are always set together. The IRO pin and its
status bit remain active until the transmitter and
the TX latch are switched off.
2. Receive mode
In this mode, the TXOWRXOF and TXRXFIFO
bits are always set together and can be cleared
by reading the STSREG. The IRO pin and its
status bit remain active until the FIFO is read (a
FIFO interrupt threshold number of bits have
been read), the receiver is switched off or the
RX FIFO is switched off.
3.9.2.4 WUTINT
The IRO pin and its status bit are cleared by reading the
STSREG.
3.9.2.5 LCEXINT
The IRO pin and its status bit follow the level of the INT pin.
3.9.2.6 LBTD
The IRO pin is released by reading the status bit of
STSREG, but the status bit remains active until the VDD
is below the threshold value.
The MRF49XA interrupt generation logic is shown in
Figure 3-7. A better way of interrupt handling is to first
read the STSREG on an interrupt and then decide the
action based on the status byte/word. It is important to
note that any of the interrupt sources can wake-up the
MRF49XA from Sleep mode. This means that the
crystal oscillator starts to supply a clock signal to the
microcontroller even if the microcontroller has its own
clock source. The MRF49XA will not enter Sleep mode
if any of the interrupt remains active, irrespective of the
state of the OSCEN bit in PMCREG. This way, the
microcontroller can always have a clock signal to
process the interrupt.
To prevent high-current consumption, which results in
short battery life, it is highly recommended to process
and clear interrupts before entering Sleep mode. The
functions which are not necessary should be turned off
to avoid unwanted interrupts. Before finalizing the micro-
controller (application) code, a thorough testing must be
conducted to make sure that all interrupt sources are
handled before putting the transceiver in Sleep mode.
The OSCEN bit controls the crystal oscillator (consider-
ing that the RXCEN and TXCEN bits are cleared) if the
CLKOEN bit (PMCREG<0>) is set. The interrupts have
no effect on it.
On interrupt, the crystal oscillator turns on automatically
to supply a clock signal to the microcontroller, irrespec-
tive of the OSCEN bit setting. The clock tail feature
provides sufficient clock pulses for the microcontroller to
enter the Low-Power Consumption mode. Due to this
automatic feature, it is not possible to turn off the crystal
by clearing the OSCEN bit if any interrupt is active.
For example, after power-on, the POR interrupt must
be cleared by a status read, and then by writing ‘0’ in
the OSCEN bit, puts the device into Sleep mode.
Note:
Before turning the OSCEN bit off, clear all
the interrupts, because the additional cur-
rent required for running the crystal oscillator
can shorten the battery life significantly.
The registers associated with interrupts are:
• STSREG (see Register 2-1)
• GENCREG (see Register 2-2)
• RXCREG (see Register 2-7)
• PMCREG (see Register 2-13)
• BCSREG (see Register 2-16)
FIGURE 3-7:
MRF49XA INTERRUPT GENERATION LOGIC
TXRXFIFO
TXCEN
TXRXFIFO
RXCEN
RESET
(Ext./Int.)
TXOWRXOF
TXCEN
IRO
TXOWRXOF
RXCEN
W U T IN T
WUTEN
LCEXINT (INT)
FINTDIO
LBTD
LBDEN
© 2009 Microchip Technology Inc.
Preliminary
DS70590B-page 53