MRF49XA Datasheet, PDF (46/102 Pages) Microchip Technology – ISM Band Sub-GHz RF Transceiver

MRF49XA
3.1.2 POWER GLITCH RESET
Spikes or glitches are found on the VDD line if the power
supply filtering is not satisfactory, or the internal resis-
tance of the power supply is very high. So, in this case,
the Sensitive Reset mode needs to be enabled. Here,
the device Reset occurs due to the transients present
on the VDD line.
The internal Reset block has two basic modes of
operation:
• Sensitive Reset Mode
• Normal Reset Mode
Sensitive Reset Mode: By enabling the Sensitive
Reset, a Reset is generated if:
• the positive going edge of the VDD has a rising
rate greater than 100 mV/ms, and
• the voltage difference between the internal ramp
signal and the VDD reaches the Reset threshold
voltage (600 mV).
The Sensitive Reset mode is the default mode which
can be changed by using the DRSTM bit (FIFOR-
STREG<0>). Figure 3-2 shows the Sensitive Reset
mode.
FIGURE 3-2:
SENSITIVE RESET ENABLED
Normal Reset Mode: The device enters this mode,
when the power glitch detection circuit is disabled.
Figure 3-3 shows the Normal Reset mode.
Note:
Negative change in the supply voltage
does not cause a Reset event unless the
VDD level reaches the Reset threshold
voltage (i.e., 250 mV in Normal Reset
mode, 1.6V in Sensitive Reset mode).
If the Sensitive mode is disabled and the power supply
is turned off, the VDD requires 250 mV to trigger a
Power-on Reset when the supply voltage is reapplied.
If the decoupling capacitors retain their charges for a
longer duration, there might be no Reset after
power-up as the power glitch detector is disabled.
Note:
The Reset event reinitializes the internal
registers, and thus, the Sensitive mode is
enabled again.
VDD
Reset Threshold
Voltage (600 mV)
1.6V
Reset Ramp Line
(100 mV/ms)
RESET ^H
Output _L
(Pin 10)
T im e
DS70590B-page 44
Preliminary
© 2009 Microchip Technology Inc.