PIC18LF4520-IPT Datasheet, PDF (54/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2420/2520/4420/4520
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
IPR2
PIR2
2420
2420
2520
2520
4420
4420
4520
4520
11-1 1111
00-0 0000
11-1 1111
00-0 0000
uu-u uuuu
uu-u uuuu⁽¹⁾
PIE2
2420 2520 4420 4520
00-0 0000
00-0 0000
uu-u uuuu
IPR1
PIR1
2420
2420
2420
2420
2520
2520
2520
2520
4420
4420
4420
4420
4520
4520
4520
4520
1111 1111
-111 1111
0000 0000
-000 0000
1111 1111
-111 1111
0000 0000
-000 0000
uuuu uuuu
-uuu uuuu
uuuu uuuu⁽¹⁾
-uuu uuuu⁽¹⁾
PIE1
2420
2420
2520
2520
4420
4420
4520
4520
0000 0000
-000 0000
0000 0000
-000 0000
uuuu uuuu
-uuu uuuu
OSCTUNE
2420 2520 4420 4520
00-0 0000
00-0 0000
uu-u uuuu
TRISE
2420 2520 4420 4520
0000 -111
0000 -111
uuuu -uuu
TRISD
2420 2520 4420 4520
1111 1111
1111 1111
uuuu uuuu
TRISC
2420 2520 4420 4520
1111 1111
1111 1111
uuuu uuuu
TRISB
TRISA⁽⁵⁾
2420
2420
2520
2520
4420
4420
4520
4520
1111 1111
1111 1111⁽⁵⁾
1111 1111
1111 1111⁽⁵⁾
uuuu uuuu
uuuu uuuu⁽⁵⁾
LATE
2420 2520 4420 4520
---- -xxx
---- -uuu
---- -uuu
LATD
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
LATA⁽⁵⁾
2420
2420
2520
2520
4420
4420
4520
4520
xxxx xxxx
xxxx xxxx⁽⁵⁾
uuuu uuuu
uuuu uuuu⁽⁵⁾
uuuu uuuu
uuuu uuuu⁽⁵⁾
PORTE
2420 2520 4420 4520
---- xxxx
---- uuuu
---- uuuu
PORTD
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
PORTA⁽⁵⁾
2420
2420
2520
2520
4420
4420
4520
4520
xxxx xxxx
xx0x 0000⁽⁵⁾
uuuu uuuu
uu0u 0000⁽⁵⁾
uuuu uuuu
uuuu uuuu⁽⁵⁾
Legend:
Note 1:
2:
3:
4:
5:
6:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When
PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.
DS39631E-page 52
© 2008 Microchip Technology Inc.