PIC18LF4520-IPT Datasheet, PDF (50/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2420/2520/4420/4520
4.6 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations, as indicated in Table 4-3. These bits
are used in software to determine the nature of the
Reset.
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Condition
Program
RCON Register
STKPTR Register
Counter
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
RESET Instruction
Brown-out Reset
0000h
1
1
1
0
0
0
0
0000h
0
u
u
u
u
u
u
0000h
1
1
1
u
0
u
u
MCLR Reset during Power-Managed
0000h
u
1
u
u
u
u
u
Run Modes
MCLR Reset during Power-Managed
0000h
u
1
0
u
u
u
u
Idle Modes and Sleep Mode
WDT Time-out during Full Power or
0000h
u
0
u
u
u
u
u
Power-Managed Run Mode
MCLR Reset during Full-Power
0000h
u
u
u
u
u
u
u
Execution
Stack Full Reset (STVREN = 1)
0000h
u
u
u
u
u
1
u
Stack Underflow Reset (STVREN = 1) 0000h
u
u
u
u
u
u
1
Stack Underflow Error (not an actual
0000h
u
u
u
u
u
u
1
Reset, STVREN = 0)
WDT Time-out during
PC + 2
u
0
0
u
u
u
u
Power-Managed Idle or Sleep Modes
Interrupt Exit from Power-Managed
PC + 2⁽¹⁾
u
u
0
u
u
u
u
Modes
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
DS39631E-page 48
© 2008 Microchip Technology Inc.