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PIC18LF4520-IPT Datasheet, PDF (51/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
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PIC18F2420/2520/4420/4520
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
TOSH
TOSL
STKPTR
2420
2420
2420
2420
2520
2520
2520
2520
4420
4420
4420
4420
4520
4520
4520
4520
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
PCLATU
2420 2520 4420 4520
---0 0000
---0 0000
---u uuuu
PCLATH
PCL
2420
2420
2520
2520
4420
4420
4520
4520
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PC + 2(2)
TBLPTRU
2420 2520 4420 4520
--00 0000
--00 0000
--uu uuuu
TBLPTRH
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
TABLAT
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
PRODH
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
INTCON
INTCON2
INTCON3
2420
2420
2420
2420
2520
2520
2520
2520
4420
4420
4420
4420
4520
4520
4520
4520
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
uuuu uuuu
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
INDF0
2420 2520 4420 4520
N/A
N/A
N/A
POSTINC0
2420 2520 4420 4520
N/A
N/A
N/A
POSTDEC0
2420 2520 4420 4520
N/A
N/A
N/A
PREINC0
2420 2520 4420 4520
N/A
N/A
N/A
PLUSW0
2420 2520 4420 4520
N/A
N/A
N/A
FSR0H
2420 2520 4420 4520
---- 0000
---- 0000
---- uuuu
FSR0L
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
2420 2520 4420 4520
N/A
N/A
N/A
POSTINC1
2420 2520 4420 4520
N/A
N/A
N/A
POSTDEC1
2420 2520 4420 4520
N/A
N/A
N/A
PREINC1
2420 2520 4420 4520
N/A
N/A
N/A
PLUSW1
2420 2520 4420 4520
N/A
N/A
N/A
Legend:
Note 1:
2:
3:
4:
5:
6:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When
PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.
© 2008 Microchip Technology Inc.
DS39631E-page 49
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