PIC18LF4520-IPT Datasheet, PDF (52/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2420/2520/4420/4520
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
2420 2520 4420 4520
---- 0000
---- 0000
---- uuuu
FSR1L
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
2420 2520 4420 4520
---- 0000
---- 0000
---- uuuu
INDF2
2420 2520 4420 4520
N/A
N/A
N/A
POSTINC2
2420 2520 4420 4520
N/A
N/A
N/A
POSTDEC2
2420 2520 4420 4520
N/A
N/A
N/A
PREINC2
2420 2520 4420 4520
N/A
N/A
N/A
PLUSW2
2420 2520 4420 4520
N/A
N/A
N/A
FSR2H
2420 2520 4420 4520
---- 0000
---- 0000
---- uuuu
FSR2L
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
2420 2520 4420 4520
---x xxxx
---u uuuu
---u uuuu
TMR0H
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
TMR0L
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
2420 2520 4420 4520
1111 1111
1111 1111
uuuu uuuu
OSCCON
2420 2520 4420 4520
0100 q000
0100 q000
uuuu quuu
HLVDCON
2420 2520 4420 4520
0-00 0101
0-00 0101
u-uu uuuu
WDTCON
RCON⁽⁴⁾
2420
2420
2520
2520
4420
4420
4520
4520
---- ---0
0q-1 11q0
---- ---0
0q-q qquu
---- ---u
uq-u qquu
TMR1H
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
2420 2520 4420 4520
0000 0000
u0uu uuuu
uuuu uuuu
TMR2
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
PR2
2420 2520 4420 4520
1111 1111
1111 1111
1111 1111
T2CON
2420 2520 4420 4520
-000 0000
-000 0000
-uuu uuuu
SSPBUF
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
SSPCON1
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
SSPCON2
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
6:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When
PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.
DS39631E-page 50
© 2008 Microchip Technology Inc.