PIC18LF4520-IPT Datasheet, PDF (53/412 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2420/2520/4420/4520
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
ADRESH
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
ADCON1
2420
2420
2520
2520
4420
4420
4520
4520
--00 0000
--00 0qqq⁽⁶⁾
--00 0000
--00 0qqq⁽⁶⁾
--uu uuuu
--uu uuuu
ADCON2
2420 2520 4420 4520
0-00 0000
0-00 0000
u-uu uuuu
CCPR1H
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
2420
2420
2520
2520
4420
4420
4520
4520
0000 0000
--00 0000
0000 0000
--00 0000
uuuu uuuu
--uu uuuu
CCPR2H
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
2420 2520 4420 4520
--00 0000
--00 0000
--uu uuuu
BAUDCON
2420 2520 4420 4520
0100 0-00
0100 0-00
uuuu u-uu
PWM1CON
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
ECCP1AS
2420
2420
2520
2520
4420
4420
4520
4520
0000 0000
0000 00--
0000 0000
0000 00--
uuuu uuuu
uuuu uu--
CVRCON
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
CMCON
2420 2520 4420 4520
0000 0111
0000 0111
uuuu uuuu
TMR3H
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
2420 2520 4420 4520
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
2420 2520 4420 4520
0000 0000
uuuu uuuu
uuuu uuuu
SPBRGH
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
SPBRG
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
RCREG
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
TXREG
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
TXSTA
2420 2520 4420 4520
0000 0010
0000 0010
uuuu uuuu
RCSTA
2420 2520 4420 4520
0000 000x
0000 000x
uuuu uuuu
EEADR
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
EEDATA
2420 2520 4420 4520
0000 0000
0000 0000
uuuu uuuu
EECON2
2420 2520 4420 4520
0000 0000
0000 0000
0000 0000
EECON1
2420 2520 4420 4520
xx-0 x000
uu-0 u000
uu-0 u000
Legend:
Note 1:
2:
3:
4:
5:
6:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit (CONFIG3H<1>). When
PBADEN = 1, PCFG<2:0> = 000; when PBADEN = 0, PCFG<2:0> = 111.
© 2008 Microchip Technology Inc.
DS39631E-page 51