RFPIC12C509AG Datasheet, PDF (53/104 Pages) Microchip Technology – 18/20-Pin 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter

rfPIC12C509AG/509AF
8.6.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writ-
ing to the OPTION register. Thus, a time-out period of
a nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see DC specs).
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several sec-
onds before a WDT time-out occurs.
8.6.2
WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device RESET.
The SLEEP instruction RESETS the WDT and the
postscaler, if assigned to the WDT. This gives the max-
imum SLEEP time before a WDT wake-up Reset.
FIGURE 8-10:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 8-5)
Watchdog
Timer
WDT Enable
Configuration
0
M
1
U
X
PSA
PPoosststsccaaleler ^r
8 - to - 1 MUX
PS2:PS0
To Timer0 (Figure 8-4)
0
1
MUX
PSA
Note: T0CS, T0SE, PSA, PS2:PS0 are bits
in the OPTION register.
WDT
Time-out
TABLE 8-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
Power-on
Reset
Value on
All Other
RESETS
N/A
OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as '0', u = unchanged
© 2001 Microchip Technology Inc.
Preliminary
DS70031A-page 51