RFPIC12C509AG Datasheet, PDF (29/104 Pages) Microchip Technology – 18/20-Pin 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter

rfPIC12C509AG/509AF
6.0 TIMER0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two instruction cycles (Figure 6-2 and
Figure 6-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge. Restric-
tions on the external clock input are discussed in detail
in Section 6.1.
The prescaler may be used by either the Timer0 mod-
ule or the Watchdog Timer, but not both. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0.
FIGURE 6-1:
TIMER0 BLOCK DIAGRAM
GP2/T0CKI
Pin
FOSC/4
T0SE
Data bus
0
PSout
8
1
Sync with
1
Internal
TMR0 reg
Programmable
Prescaler⁽²⁾
0
Clocks
PSout
(2 TCY delay) ^Sync
T0CS⁽¹⁾
3
PS2, PS1, PS0⁽¹⁾
PSA⁽¹⁾
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
© 2001 Microchip Technology Inc.
Preliminary
DS70031A-page 27