RFPIC12C509AG Datasheet, PDF(15/104 Page) Microchip Technology – 18/20-Pin 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter

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RFPIC12C509AG Datasheet, PDF (15/104 Pages) Microchip Technology – 18/20-Pin 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter

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rfPIC12C509AG/509AF

3.3 Clocking Scheme/Instruction

Cycle

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram counter is incremented every Q1, and the instruc-

tion is fetched from program memory and latched into

instruction register in Q4. It is decoded and executed

during the following Q1 through Q4. The clocks and

instruction execution flow is shown in Figure 3-2 and

Example 3-1.

FIGURE 3-2:

CLOCK/INSTRUCTION CYCLE

3.4 Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

Q1 Q2 Q3 Q4

OSC1

Fetch INST (PC)

Execute INST (PC-1)

Q1 Q2 Q3 Q4

PC+1

Fetch INST (PC+1)

Execute INST (PC)

Q1 Q2 Q3 Q4

PC+2

Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF GPIO

3. CALL SUB_1

4. BSF GPIO, BIT1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is âflushedâ from the pipeline while the new instruction is being fetched and then executed.

Preliminary

DS70031A-page 13

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