PIC16F87_05 Datasheet, PDF (51/228 Pages) Microchip Technology – 18/20/28-Pin Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F87/88
TABLE 4-4: CLOCK SWITCHING MODES
Current
System
Clock
SCS Bits <1:0>
Modified to:
Delay
OSTS IOFS T1RUN
Bit Bit Bit
New
System
Clock
Comments
LP, XT, HS,
10
8 Clocks of 0
1⁽¹⁾
T1OSC,
(INTRC)
INTRC
EC, RC FOSC<2:0> = LP,
XT or HS
0
INTRC The internal RC oscillator
or
frequency is dependant upon
INTOSC the IRCF bits.
or
INTOSC
Postscaler
LP, XT, HS,
01
8 Clocks of 0
N/A
1
INTRC,
(T1OSC)
T1OSC
EC, RC FOSC<2:0> = LP,
XT or HS
T1OSC T1OSCEN bit must be
enabled.
INTRC
00
8 Clocks of 1
N/A
0
EC
T1OSC FOSC<2:0> = EC
EC
or
or
or
RC
FOSC<2:0> = RC
RC
INTRC
00
1024 Clocks 1
N/A
0 LP, XT, HS During the 1024 clocks,
T1OSC FOSC<2:0> = LP, (OST)
program execution is clocked
XT, HS
+
from the secondary oscillator
8 Clocks of
until the primary oscillator
LP, XT, HS
becomes stable.
LP, XT, HS
00
1024 Clocks 1
N/A
0 LP, XT, HS When a Reset occurs, there is
(Due to Reset)
(OST)
no clock transition sequence.
LP, XT, HS
Instruction execution and/or
peripheral operation is
suspended unless Two-Speed
Start-up mode is enabled, after
which the INTRC will act as the
system clock until the OST
timer has expired.
Note 1: If the new clock source is the INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms (approx.)
after the clock change.
 2005 Microchip Technology Inc.
DS30487C-page 49