PIC16F87_05 Datasheet, PDF (126/228 Pages) Microchip Technology – 18/20/28-Pin Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F87/88
FIGURE 13-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
CnINV
To Data Bus
Q
D
RD_CMCON
EN
Q1
Set CMIF bit
From other Comparator
Q
D
EN
CL
RESET
Q3 * RD_CMCON
13.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2 register) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it (‘0’). Since it is
also possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE2 register) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2
register) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
DS30487C-page 124
 2005 Microchip Technology Inc.