PIC16F87_05 Datasheet, PDF (18/228 Pages) Microchip Technology – 18/20/28-Pin Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F87/88
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Details
on
page
Bank 2
100h⁽²⁾ INDF
101h
102h⁽²⁾
103h⁽²⁾
104h⁽²⁾
TMR0
PCL
STATUS
FSR
105h WDTCON
106h PORTB
107h
—
108h
—
109h
—
10Ah^(1,2) PCLATH
10Bh⁽²⁾ INTCON
10Ch
10Dh
10Eh
10Fh
EEDATA
EEADR
EEDATH
EEADRH
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN
PORTB Data Latch when written; PORTB pins when read (PIC16F87)
PORTB Data Latch when written; PORTB pins when read (PIC16F88)
Unimplemented
Unimplemented
Unimplemented
—
—
—
Write Buffer for the Upper 5 bits of the Program Counter
GIE
PEIE
TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
EEPROM/Flash Data Register Low Byte
EEPROM/Flash Address Register Low Byte
—
— EEPROM/Flash Data Register High Byte
—
—
—
—
EEPROM/Flash Address Register High Byte
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
---0 1000
xxxx xxxx
00xx xxxx
—
—
—
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
--xx xxxx
---- xxxx
26, 135
69
135
17
135
142
58
—
—
—
135
19, 69,
77
34
34
34
34
Bank 3
180h⁽²⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 135
181h
182h⁽²⁾
183h⁽²⁾
184h⁽²⁾
OPTION_REG RBPU INTEDG T0CS
T0SE
PCL
Program Counter (PC) Least Significant Byte
STATUS
IRP
RP1
RP0
TO
FSR
Indirect Data Memory Address Pointer
PSA
PD
PS2
PS1
PS0 1111 1111 18, 69
0000 0000 135
Z
DC
C
0001 1xxx 17
xxxx xxxx ¹³⁵
185h
—
Unimplemented
—
—
186h TRISB
PORTB Data Direction Register
1111 1111 58, 83
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
18Ah^(1,2) PCLATH
18Bh⁽²⁾ INTCON
Unimplemented
—
—
GIE
PEIE
—
Write Buffer for the Upper 5 bits of the Program Counter
TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
—
---0 0000
0000 000x
—
135
19, 69,
77
18Ch EECON1
EEPGD
—
—
FREE
WRERR
WREN
WR
RD
x--x x000 28, 34
18Dh EECON2
EEPROM Control Register 2 (not a physical register)
---- ---- 34
18Eh
—
Reserved, maintain clear
0000 0000 —
18Fh
—
Reserved, maintain clear
0000 0000 —
Legend:
Note 1:
2:
3:
4:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
PIC16F88 device only.
DS30487C-page 16
 2005 Microchip Technology Inc.