PIC16F87_05 Datasheet, PDF (217/228 Pages) Microchip Technology – 18/20/28-Pin Enhanced Flash Microcontrollers with nanoWatt Technology

INDEX
A
A/D
Acquisition Requirements ........................................ 117
ADIF Bit .................................................................... 116
Analog-to-Digital Converter ...................................... 113
Associated Registers ............................................... 120
Calculating Acquisition Time .................................... 117
Configuring Analog Port Pins ................................... 119
Configuring the Interrupt .......................................... 116
Configuring the Module ............................................ 116
Conversion Clock ..................................................... 118
Conversions ............................................................. 119
Converter Characteristics ........................................ 190
Delays ...................................................................... 117
Effects of a Reset ..................................................... 120
GO/DONE Bit ........................................................... 116
Internal Sampling Switch (Rss) Impedance ............. 117
Operation During Sleep ........................................... 120
Operation in Power-Managed Modes ...................... 118
Result Registers ....................................................... 119
Source Impedance ................................................... 117
Time Delays ............................................................. 117
Using the CCP Trigger ............................................. 120
Absolute Maximum Ratings ............................................. 163
ACK .................................................................................... 93
ADCON0 Register ...................................................... 14, 113
ADCON1 Register ...................................................... 15, 113
Addressable Universal Synchronous Asynchronous
Receiver Transmitter. See AUSART.
ADRESH Register ...................................................... 14, 113
ADRESH, ADRESL Register Pair .................................... 116
ADRESL Register ...................................................... 15, 113
ANSEL Register ............................................. 15, 52, 58, 113
Application Notes
AN556 (Implementing a Table Read) ........................ 25
AN578 (Use of the SSP Module in the I²C
Multi-Master Environment) ................................. 87
AN607 (Power-up Trouble Shooting) ....................... 133
Assembler
MPASM Assembler .................................................. 157
Asynchronous Reception
Associated Registers ....................................... 105, 107
Asynchronous Transmission
Associated Registers ............................................... 103
AUSART ............................................................................ 97
Address Detect Enable (ADDEN Bit) ......................... 98
Asynchronous Mode ................................................ 102
Asynchronous Receive (9-bit Mode) ........................ 106
Asynchronous Receive with Address Detect.
See Asynchronous Receive (9-Bit Mode).
Asynchronous Receiver ........................................... 104
Asynchronous Reception ......................................... 105
Asynchronous Transmitter ....................................... 102
Baud Rate Generator (BRG) ...................................... 99
Baud Rate Formula ............................................ 99
Baud Rates, Asynchronous Mode
(BRGH = 0) .............................................. 100
Baud Rates, Asynchronous Mode
(BRGH = 1) .............................................. 100
High Baud Rate Select (BRGH Bit) ................... 97
PIC16F87/88
INTRC Baud Rates, Asynchronous Mode
(BRGH = 0) .............................................. 101
INTRC Baud Rates, Asynchronous Mode
(BRGH = 1) .............................................. 101
INTRC Operation ............................................... 99
Low-Power Mode Operation .............................. 99
Sampling ........................................................... 99
Clock Source Select (CSRC Bit) ............................... 97
Continuous Receive Enable (CREN Bit) ................... 98
Framing Error (FERR Bit) .......................................... 98
Mode Select (SYNC Bit) ............................................ 97
Receive Data, 9th bit (RX9D Bit) ............................... 98
Receive Enable, 9-bit (RX9 Bit) ................................. 98
Serial Port Enable (SPEN Bit) ............................. 97, 98
Single Receive Enable (SREN Bit) ............................ 98
Synchronous Master Mode ...................................... 108
Synchronous Master Reception .............................. 110
Synchronous Master Transmission ......................... 108
Synchronous Slave Mode ........................................ 111
Synchronous Slave Reception ................................ 112
Synchronous Slave Transmit ................................... 111
Transmit Data, 9th Bit (TX9D) ................................... 97
Transmit Enable (TXEN Bit) ...................................... 97
Transmit Enable, Nine-bit (TX9 Bit) ........................... 97
Transmit Shift Register Status
(TRMT Bit) ......................................................... 97
B
Baud Rate Generator
Associated Registers ................................................. 99
BF Bit ................................................................................. 93
Block Diagrams
A/D ........................................................................... 116
Analog Input Model .......................................... 117, 125
AUSART Receive ............................................ 104, 106
AUSART Transmit ................................................... 102
Capture Mode Operation ........................................... 82
Comparator I/O Operating Modes ........................... 122
Comparator Output .................................................. 124
Comparator Voltage Reference ............................... 128
Compare Mode Operation ......................................... 83
Fail-Safe Clock Monitor ........................................... 144
In-Circuit Serial Programming
Connections .................................................... 147
Interrupt Logic .......................................................... 139
On-Chip Reset Circuit .............................................. 132
PIC16F87 .................................................................... 6
PIC16F88 .................................................................... 7
RA0/AN0:RA1/AN1 Pins ............................................ 52
RA2/AN2/CVREF/VREF- Pin ....................................... 53
RA3/AN3/VREF+/C1OUT Pin ..................................... 53
RA4/AN4/T0CKI/C2OUT Pin ..................................... 54
RA5/MCLR/VPP Pin ................................................... 54
RA6/OSC2/CLKO Pin ................................................ 55
RA7/OSC1/CLKI Pin .................................................. 56
RB0/INT/CCP1 Pin .................................................... 59
RB1/SDI/SDA Pin ...................................................... 60
RB2/SDO/RX/DT Pin ................................................. 61
RB3/PGM/CCP1 Pin .................................................. 62
RB4/SCK/SCL Pin ..................................................... 63
RB5/SS/TX/CK Pin .................................................... 64
 2005 Microchip Technology Inc.
DS30487C-page 215