PIC16F720_13 Datasheet, PDF (28/254 Pages) Microchip Technology – 20-Pin Flash Microcontrollers

PIC16(L)F720/721
3.4.2 WDT CONTROL
The WDTEN bit is located in the Configuration Word
Register 1. When set, the WDT runs continuously.
The PSA and PS<2:0> bits of the OPTION_REG
register control the WDT period. See Section 12.0
“Timer0 Module” for more information.
FIGURE 3-3: WATCHDOG TIMER BLOCK DIAGRAM
T1GSS = 11
TMR1GE
WDTEN
From TMR0
Clock Source
Low-Power
WDT OSC
0
Divide by
512
1
PSA
TABLE 3-3: WDT STATUS
Conditions
WDTEN = 0
CLRWDT Command
Exit Sleep + System Clock = INTOSC, EXTCLK
Postscaler
8
0
1
To T1G
WDTEN
PS<2:0>
TO TMR0
WDT Reset
WDT
Cleared
DS41430D-page 28
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