PIC16F720_13 Datasheet, PDF (133/254 Pages) Microchip Technology – 20-Pin Flash Microcontrollers

PIC16(L)F720/721
FIGURE 16-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
INTCON
GIE
PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF
38
PIE1
TMR1GIE ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE
39
PIR1
TMR1GIF ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
40
RCREG
AUSART Receive Data Register
123
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
126
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
61
TXSTA
CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D
125
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous master
reception.
 2010-2013 Microchip Technology Inc.
DS41430D-page 133