PIC16F720_13 Datasheet, PDF (121/254 Pages) Microchip Technology – 20-Pin Flash Microcontrollers

PIC16(L)F720/721
FIGURE 16-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
BRG Output
(Shift Clock)
TX/CK pin
TXIF bit
(Transmit Buffer
Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
1 TCY
Start bit
Word 1
Transmit Shift Reg.
bit 0
1 TCY
bit 1
Word 1
bit 7/8 _{Stop bit}
Start bit
bit 0
Word 2
Word 2
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 16-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
INTCON
GIE
PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF
38
PIE1
TMR1GIE ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE
39
PIR1
TMR1GIF ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
40
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
126
SPBRG
BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0
127
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
61
TXREG
AUSART Transmit Data Register
—
TXSTA
CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D
125
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for asynchronous transmission.
16.1.2 AUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 16-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to a two character First-In
First-Out (FIFO) memory. The FIFO buffering allows
reception of two complete characters and the start of a
third character before software must start servicing the
AUSART receiver. The FIFO and RSR registers are not
directly accessible by software. Access to the received
data is via the RCREG register.
16.1.2.1 Enabling the Receiver
The AUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other AUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the AUSART. Clearing the SYNC bit
of the TXSTA register configures the AUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the AUSART and automatically
configures the RX/DT I/O pin as an input.
Note:
When the SPEN bit is set, the TX/CK I/O
pin is automatically configured as an
output, regardless of the state of the
corresponding TRIS bit and whether or
not the AUSART transmitter is enabled.
The PORT latch is disconnected from the
output driver so it is not possible to use the
TX/CK pin as a general purpose output.
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DS41430D-page 121