PIC16LF1503 Datasheet, PDF (245/340 Pages) Microchip Technology – 14-Pin Flash, 8-Bit Microcontrollers

24.5 Interrupts
When the accumulator overflows, the NCOx Interrupt
Flag bit, NCOxIF, of the PIRx register is set. To enable
the interrupt event, the following bits must be set:
• NxEN bit of the NCOxCON register
• NCOxIE bit of the PIEx register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt must be cleared by software by clearing
the NCOxIF bit in the Interrupt Service Routine.
24.6 Effects of a Reset
All of the NCOx registers are cleared to zero as the
result of a Reset.
24.7 Operation In Sleep
The NCO module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock source selected remains
active.
The HFINTOSC remains active during Sleep when the
NCO module is enabled and the HFINTOSC is
selected as the clock source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the NCO clock
source, when the NCO is enabled, the CPU will go idle
during Sleep, but the NCO will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
24.8 Alternate Pin Locations
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 11.1 “Alternate Pin Function” for
more information.
PIC16(L)F1503
 2011 Microchip Technology Inc.
Preliminary
DS41607A-page 245