PIC16LF1503 Datasheet, PDF (174/340 Pages) Microchip Technology – 14-Pin Flash, 8-Bit Microcontrollers

PIC16(L)F1503
21.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx inter-
rupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
21.2.7 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 11.1 “Alternate Pin Function” for
more information.
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
—
—
—
ANSA4
ANSA3
ANSA2 ANSA1 ANSA0
APFCON
—
—
SDOSEL SSSEL T1GSEL
—
CLC1SEL NCO1SEL
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE ADIE
—
—
SSP1IE
—
TMR2IE TMR1IE
PIR1
TMR1GIF ADIF
—
—
SSP1IF
—
TMR2IF TMR1IF
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON1 WCOL
SSPOV SSPEN
CKP
SSPM<3:0>
SSPCON3 ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
SSPSTAT
TRISA
SMP
—
CKE
—
D/A
TRISA5
P
TRISA4
S
—⁽¹⁾
R/W
TRISA2
UA
TRISA1
BF
TRISA0
TRISC
—
—
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
Legend:
*
Note 1:
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.
Page provides register information.
Unimplemented, read as ‘1’.
103
100
66
67
70
168*
213
215
212
102
106
DS41607A-page 174
Preliminary
 2011 Microchip Technology Inc.