PIC16LF1503 Datasheet, PDF (168/340 Pages) Microchip Technology – 14-Pin Flash, 8-Bit Microcontrollers

PIC16(L)F1503
FIGURE 21-4:
SPI MASTER AND MULTIPLE SLAVE CONNECTION
SPI Master
SCKx
SDOx
SDIx
General I/O
General I/O
General I/O
SCKx
SDIx
SDOx
SSx
SPI Slave
#1
SCKx
SDIx
SDOx
SSx
SPI Slave
#2
SCKx
SDIx
SDOx
SSx
SPI Slave
#3
21.2.1 SPI MODE REGISTERS
The MSSPx module has five registers for SPI mode
operation. These are:
• MSSPx STATUS register (SSPxSTAT)
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Control Register 3 (SSPxCON3)
• MSSPx Data Buffer register (SSPxBUF)
• MSSPx Address register (SSPxADD)
• MSSPx Shift register (SSPxSR)
(Not directly accessible)
SSPxCON1 and SSPxSTAT are the control and
STATUS registers in SPI mode operation. The
SSPxCON1 register is readable and writable. The
lower 6 bits of the SSPxSTAT are read-only. The upper
two bits of the SSPxSTAT are read/write.
In one SPI master mode, SSPxADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 21.7 “Baud Rate Generator”.
SSPxSR is the shift register used for shifting data in
and out. SSPxBUF provides indirect access to the
SSPxSR register. SSPxBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSPxSR and SSPxBUF
together create a buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPxSR.
DS41607A-page 168
Preliminary
 2011 Microchip Technology Inc.