PIC16LF1503 Datasheet, PDF (196/340 Pages) Microchip Technology – 14-Pin Flash, 8-Bit Microcontrollers

PIC16(L)F1503
21.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<7:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 21-25).
FIGURE 21-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDAx
DX
DX ‚ – 1
SCLx
BRG
Value
BRG
Reload
SCLx deasserted but slave holds
SCLx low (clock arbitration)
SCLx allowed to transition high
BRG decrements on
Q2 and Q4 cycles
03h
02h
01h
00h (hold off)
SCLx is sampled high, reload takes
place and BRG starts its count
03h
02h
21.6.3 WCOL STATUS FLAG
If the user writes the SSPxBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL bit is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not Idle.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
DS41607A-page 196
Preliminary
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