PIC16LC74B-16 Datasheet, PDF (23/41 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

PIC16LC74B-16/PTL16
FIGURE 2-15: I²C BUS DATA TIMING
103
SCL
SDA
In
90
91
100
106
101
107
109
109
SDA
Out
Note: Refer to Figure 2-2 for load conditions.
102
92
110
TABLE 2-13: I²C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Max Units
Conditions
100*
101*
102*
103*
90*
91*
106*
107*
92*
109*
110*
*
Note 1:
2:
THIGH
Clock high time
100 kHz mode
4.0
—
µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
µs Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
—
TLOW
Clock low time
100 kHz mode
4.7
—
µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
µs Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
—
TR
SDA and SCL rise
100 kHz mode
—
1000 ns
time
400 kHz mode
20 + 0.1Cb 300
ns Cb is specified to be from
10-400 pF
TF
SDA and SCL fall time 100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1Cb 300
ns Cb is specified to be from
10-400 pF
TSU:STA
START condition
setup time
100 kHz mode
400 kHz mode
4.7
—
µs Only relevant for repeated
0.6
—
µs ^{START condition}
THD:STA
START condition hold 100 kHz mode
time
400 kHz mode
4.0
—
µs After this period the first clock
0.6
—
µs pulse is generated
THD:DAT Data input hold time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
µs
TSU:DAT Data input setup time 100 kHz mode
250
—
ns Note 2
400 kHz mode
100
—
ns
TSU:STO STOP condition setup 100 kHz mode
4.7
—
µs
time
400 kHz mode
0.6
—
µs
TAA
Output valid from
100 kHz mode
—
3500 ns Note 1
clock
400 kHz mode
—
—
ns
TBUF
Bus free time
100 kHz mode
400 kHz mode
4.7
—
µs Time the bus must be free
1.3
—
µs ^{before a new transmission can}
start
Cb
Bus capacitive loading
—
400 pF
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the requirement
Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line TR max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before the SCL line
is released.
© 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 23