PIC16LC74B-16 Datasheet, PDF (19/41 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

PIC16LC74B-16/PTL16
FIGURE 2-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
74
Note: Refer to Figure 2.1 for load conditions.
LSb IN
TABLE 2-9: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Typ† Max Units Conditions
71
TscH
71A
SCK input high time
(slave mode)
Continuous
Single Byte
1.25TCY + 30 — — ns
40
— — ns Note 1
72
TscL
72A
SCK input low time
(slave mode)
Continuous
Single Byte
1.25TCY + 30 — — ns
40
— — ns Note 1
73
TdiV2scH, Setup time of SDI data input to SCK
TdiV2scL edge
100
— — ns
73A
TB2B
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns Note 1
edge of Byte2
74
TscH2diL, Hold time of SDI data input to SCK edge
100
TscL2diL
— — ns
75
TdoR
SDO data output rise time
20 45 ns
76
TdoF
SDO data output fall time
—
10 25 ns
78
TscR
SCK output rise time (master mode)
20 45 ns
79
TscF
SCK output fall time (master mode)
—
10 25 ns
80
TscH2doV, SDO data output valid after SCK edge
TscL2doV
— 100 ns
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
— — ns
† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
© 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 19