|
PIC16LC74B-16 Datasheet, PDF (21/41 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter | |||
|
◁ |
PIC16LC74B-16/PTL16
FIGURE 2-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
77
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Typâ Max Units Conditions
70
TssL2scH, SSâ to SCKâ or SCKâ input
TssL2scL
TCY
â â ns
71
TscH
71A
SCK input high time
(slave mode)
Continuous
Single Byte
1.25TCY + 30 â â ns
40
â â ns Note 1
72
TscL
72A
SCK input low time
(slave mode)
Continuous
Single Byte
1.25TCY + 30 â â ns
40
â â ns Note 1
73A
TB2B
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 â â ns Note 1
edge of Byte2
74
TscH2diL, Hold time of SDI data input to SCK edge
100
TscL2diL
â â ns
75
TdoR
SDO data output rise time
20 45 ns
76
TdoF
SDO data output fall time
â
10 25 ns
77
TssH2doZ SSâ to SDO output hi-impedance
10
â 50 ns
78
TscR
SCK output rise time (master mode)
â
20 45 ns
79
TscF
SCK output fall time (master mode)
â
10 25 ns
80
TscH2doV, SDO data output valid after SCK edge
TscL2doV
â
â 100 ns
82
TssL2doV SDO data output valid after SSâ edge
â
â 100 ns
83
TscH2ssH, SS â after SCK edge
TscL2ssH
1.5TCY + 40 â â ns
â Data in âTypâ column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
© 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 21
|
▷ |