PIC16F87XA Datasheet, PDF (197/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
FIGURE 17-19: A/D CONVERSION TIMING
BSF ADCON0, GO
Q4
A/D CLK 132
A/D DATA
ADRES
ADIF
GO
(TOSC/2)⁽¹⁾
1 TCY
131
130
9
8
7 ^{... ...}
2
1
0
OLD_DATA
NEW_DATA
DONE
SAMPLE
Sampling Stopped
Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 17-15: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
130 TAD
A/D Clock Period
PIC16F87XA
1.6
PIC16LF87XA
3.0
PIC16F87XA
2.0
PIC16LF87XA
3.0
131 TCNV Conversion Time (not including S/H time)
(Note 1)
132 TACQ Acquisition Time
(Note 2)
Typ†
—
—
4.0
6.0
—
40
Max Units
Conditions
—
µs TOSC based, VREF ≥ 3.0V
—
µs TOSC based, VREF ≥ 2.0V
6.0 µs A/D RC mode
9.0 µs A/D RC mode
12 TAD
—
µs
10*
—
—
µs The minimum time is the
amplifier settling time. This may
be used if the “new” input volt-
age has not changed by more
than 1 LSb (i.e., 20.0 mV @
5.12V) from the last sampled
voltage (as stated on CHOLD).
134 TGO Q4 to A/D Clock Start
— TOSC/2 § —
— If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.1 “A/D Acquisition Requirements” for minimum conditions.
 2003 Microchip Technology Inc.
DS39582B-page 195