PIC16F87XA Datasheet, PDF (140/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
FIGURE 12-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+-
CxINV
To RA4 or
RA5 Pin
Bus
Data
Q
D
Read CMCON
EN
Set
CMIF
bit
From
Other
Comparator
Q
D
EN
CL
Read CMCON
Reset
12.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it (‘0’). Since it is
also possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
DS39582B-page 138
 2003 Microchip Technology Inc.