PIC16F87XA Datasheet, PDF (150/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
14.4 MCLR
PIC16F87XA devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
differs from previous devices of this family. Voltages
applied to the pin that exceed its specification can
result in both Resets and current consumption outside
of device specification during the Reset event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to VDD. The use of an RCR
network, as shown in Figure 14-5, is suggested.
FIGURE 14-5:
VDD
RECOMMENDED MCLR
CIRCUIT
PIC16F87XA
R1⁽¹⁾
R2⁽²⁾
C1
MCLR
Note 1:
2:
R1 < 40 kΩ is recommended to make
sure that the voltage drop across R does
not violate the device’s electrical
specification.
R2 > than 1K will limit any current
flowing into MCLR from the external
capacitor C, in the event of MCLR/VPP
breakdown due to Electrostatic
Discharge (ESD) or Electrical
Overstress (EOS).
14.5 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V-1.7V). To take
advantage of the POR, tie the MCLR pin to VDD
through an RC network, as described in Section 14.4
“MCLR”. A maximum rise time for VDD is specified.
See Section 17.0 “Electrical Characteristics” for
details.
When the device starts normal operation (exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating condi-
tions are met. Brown-out Reset may be used to meet
the start-up conditions. For additional information, refer
to application note, AN607, “Power-up Trouble
Shooting” (DS00607).
DS39582B-page 148
14.6 Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in Reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable or
disable the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See
Section 17.0 “Electrical Characteristics” for details
(TPWRT, parameter #33).
14.7 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a delay of
1024 oscillator cycles (from OSC1 input) after the
PWRT delay is over (if PWRT is enabled). This helps to
ensure that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
14.8 Brown-out Reset (BOR)
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100 µS), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a Reset may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in Reset for
TPWRT (parameter #33, about 72 mS). If VDD should
fall below VBOR during TPWRT, the Brown-out Reset
process will restart when VDD rises above VBOR with
the Power-up Timer Reset. The Power-up Timer is
always enabled when the Brown-out Reset circuit is
enabled, regardless of the state of the PWRT
configuration bit.
14.9 Time-out Sequence
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR Reset
occurs. Then, OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of Reset.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution
immediately. This is useful for testing purposes or to
synchronize more than one PIC16F87XA device
operating in parallel.
Table 14-5 shows the Reset conditions for the Status,
PCON and PC registers, while Table 14-6 shows the
Reset conditions for all the registers.
 2003 Microchip Technology Inc.