PIC16F87XA Datasheet, PDF (122/234 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers

PIC16F87XA
FIGURE 10-7:
RC7/RX/DT
(pin)
Load RSR
Read
RCIF
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
Start
bit bit 0 bit 1
Start
bit 8 Stop bit bit 0
bit
bit 8 Stop
bit
Bit 8 = 0, Data Byte
Bit 8 = 1, Address Byte
Word 1
RCREG
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN = 1.
FIGURE 10-8:
RC7/RX/DT
(pin)
Load RSR
Read
RCIF
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start
bit bit 0 bit 1
Start
bit 8 Stop bit bit 0
bit
bit 8 Stop
bit
Bit 8 = 1, Address Byte
Bit 8 = 0, Data Byte
Word 1
RCREG
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
GIE
PSPIF⁽¹⁾
PEIE TMR0IE INTE
ADIF RCIF TXIF
RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah
RCREG USART Receive Register
0000 0000 0000 0000
8Ch
PIE1
PSPIE⁽¹⁾ ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h
TXSTA
CSRC TX9 TXEN SYNC —
BRGH TRMT TX9D 0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
DS39582B-page 120
 2003 Microchip Technology Inc.