PIC18F14K22LIN Datasheet, PDF (17/62 Pages) Microchip Technology – 20-Pin Flash Microcontrollers 20-Pin Flash Microcontrollers

PIC18F14K22LIN
TABLE 2-2: REGISTER FILE SUMMARY (PIC18F14K22LIN) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on POR,
BOR
SPBRGH
EUSART Baud Rate Generator Register, High Byte
0000 0000
SPBRG
EUSART Baud Rate Generator Register, Low Byte
0000 0000
RCREG
EUSART Receive Register
0000 0000
TXREG
TXSTA⁽³⁾
RCSTA⁽³⁾
EUSART Transmit Register
0
0
SPEN
0
TXEN
0
0
CREN
SENDB
0
BRGH
FERR
TRMT
OERR
0000 0000
0
0000 0010
0
0000 000x
EEADR
EEADR7
EEADR6
EEADR5 EEADR4
EEADR3
EEADR2
EEADR1 EEADR0 0000 0000
EEADRH
—
—
—
—
—
—
EEADR9 EEADR8 ---- --00
EEDATA
EEPROM Data Register
0000 0000
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCLIP
—
TMR3IP
—
1111 111-
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCLIF
—
TMR3IF
—
0000 000-
PIE2
IPR1⁽³⁾
PIR1⁽³⁾
PIE1⁽³⁾
OSCFIE
—
—
—
C1IE
ADIP
ADIF
ADIE
C2IE
RCIP
RCIF
RCIE
EEIE
TXIP
TXIF
TXIE
BCLIE
1
0
0
—
CCP1IP
CCP1IF
CCP1IE
TMR3IE
TMR2IP
TMR2IF
TMR2IE
—
TMR1IP
TMR1IF
TMR1IE
0000 000-
-111 1111
-000 0000
-000 0000
OSCTUNE
TRISC⁽³⁾
TRISB⁽³⁾
INTSRC
TRISC7
TRISB7
PLLEN
—
TRISB6
TUN5
TRISC5
TRISB5
TUN4
TRISC4
TRISB4
TUN3
TRISC3
—
TUN2
TRISC2
—
TUN1
TRISC1
—
TUN0
TRISC0
—
0000 0000
1111 1111
1111 ----
TRISA
LATC⁽³⁾
LATB⁽³⁾
—
LINRESET
LATB7
—
—
LATB6
TRISA5
LATC5
LATB5
TRISA4
LATC4
LATB4
—
LATC3
—
TRISA2
LATC2
—
TRISA1
LATC1
—
TRISA0
LATC0
—
--11 -111
xxxx xxxx
xxxx ----
LATA
PORTC⁽³⁾
PORTB⁽³⁾
—
LINRESET
LINTX
—
—
LINCS
LATA5
RC5
LINRX
LATA4
RC4
RB4
—
RC3
—
LATA2
RC2
—
LATA1
RC1
—
LATA0
RC0
—
--xx -xxx
xxxx xxxx
xxxx ----
PORTA
—
ANSELH⁽³⁾
—
—
RA5
RA4
RA3⁽²⁾
RA2
RA1
RA0
--xx xxxx
—
—
—
0
ANS10
0
0
---- 1111
ANSEL
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
—
—
—
—
0000 ----
IOCA
—
—
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
--00 0000
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
—
—
—
—
1111 ----
WPUA
—
—
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
--11 1111
SLRCON
—
—
—
—
—
Reserved Reserved Reserved ---- -111
SSPMSK⁽³⁾
1
1
1
1
1
1
1
1
1111 1111
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH1
C1CH0
0000 1000
CM2CON1
MC1OUT MC2OUT C1RSEL C2RSEL
C1HYS
C2HYS
C1SYNC C2SYNC 0000 0000
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH1
C2CH0
0000 1000
SRCON1
SRSPE
SRSCKE SRSC2E SRSC1E
SRRPE
SRRCKE SRRC2E SRRC1E 0000 0000
SRCON0
SRLEN
SRCLK2
SRCLK1 SRCLK0
SRQEN
SRNQEN
SRPS
SRPR
0000 0000
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. Refer to
DS41365, “PIC18(L)F1XK22 Data Sheet”, Section 21.4 “Brown-out Reset (BOR)” for additional information
The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit
is read-only.
Rows highlighted in black show required values for normal LIN protocol applications.
 2011 Microchip Technology Inc.
Preliminary
DS41580A-page 21