PIC18F14K22LIN Datasheet, PDF (15/62 Pages) Microchip Technology – 20-Pin Flash Microcontrollers 20-Pin Flash Microcontrollers

PIC18F14K22LIN
TABLE 2-2: REGISTER FILE SUMMARY (PIC18F14K22LIN)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on POR,
BOR
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
TOSH
Top-of-Stack, High Byte (TOS<15:8>)
0000 0000
TOSL
Top-of-Stack, Low Byte (TOS<7:0>)
0000 0000
STKPTR
STKOVF STKUNF
—
SP4
SP3
SP2
SP1
SP0
00-0 0000
PCLATU
—
—
—
Holding Register for PC<20:16>
---0 0000
PCLATH
Holding Register for PC<15:8>
0000 0000
PCL
PC, Low Byte (PC<7:0>)
0000 0000
TBLPTRU
—
—
—
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
---0 0000
TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>)
0000 0000
TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>)
0000 0000
TABLAT
Program Memory Table Latch
0000 0000
PRODH
Product Register, High Byte
xxxx xxxx
PRODL
Product Register, Low Byte
xxxx xxxx
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RABIE
TMR0IF
INT0IF
RABIF
0000 000x
INTCON2
RABPU
INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
RABIP
1111 -1-1
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
11-0 0-00
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of
N/A
FSR0 offset by W
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0, High Byte
---- 0000
FSR0L
Indirect Data Memory Address Pointer 0, Low Byte
xxxx xxxx
WREG
Working Register
xxxx xxxx
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of
N/A
FSR1 offset by W
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1, High Byte
---- 0000
FSR1L
Indirect Data Memory Address Pointer 1, Low Byte
xxxx xxxx
BSR
—
—
—
—
Bank Select Register
---- 0000
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of
N/A
FSR2 offset by W
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2, High Byte
---- 0000
FSR2L
Indirect Data Memory Address Pointer 2, Low Byte
xxxx xxxx
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. Refer to
DS41365, “PIC18(L)F1XK22 Data Sheet”, Section 21.4 “Brown-out Reset (BOR)” for additional information
The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit
is read-only.
Rows highlighted in black show required values for normal LIN protocol applications.
 2011 Microchip Technology Inc.
Preliminary
DS41580A-page 19