TH8062 Datasheet, PDF (17/38 Pages) Melexis Microelectronic Systems – Voltage Regulator with LIN Transceiver

TH8062
Voltage Regulator with LIN Transceiver
3.6 LIN BUS Transceiver
The TH8062 has an integrated bi-directional bus interface device for data transfer between LIN bus and the
LIN protocol controller.
The transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver
with high voltage comparator followed by a debouncing unit.
Transmit Mode
During transmission the data at the pin TxD will be transferred to the BUS driver to generate a bus signal. To
minimize the electromagnetic emission of the bus line, the BUS driver has an integrated slew rate control
and wave shaping unit.
Transmitting will be interrupted in the following cases:
- Sleep mode
- Thermal Shutdown active
- Master Reset (V_CC < 3.15V)
The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode
This diode prevents the reverse current of V_BUS during differential voltage between VSUP and BUS
(V_BUS>V_SUP).
No additional termination resistor is necessary to use the TH8062 in LIN slave nodes. If this IC is used for
LIN master nodes it is necessary that the BUS pin is terminated via an external 1kΩ resistor in series with a
diode to VBAT.
Receive Mode
The data signals from the BUS pin will be transferred continuously to the pin RxD. Short spikes on the bus
signal are suppressed by the implemented debouncing circuit (τ = 2.8µs).
VSUP
60%
BUS ^50%
40%
RxD
V_{thr_max}
V_{thr_hys}
V_{thr_min}
Vthr_cnt
t < t_{deb_BUS}
t < t_{deb_BUS}
Figure 7 - Receive mode impulse diagram
The receive threshold values V_{thr_max} and V_{thr_min} are symmetrical to the centre voltage of 0.5*V_SUP with a
hysteresis of 0.175*V_SUP. Including all tolerances the LIN specific receive threshold values of 0.4*V_SUP and
0.6*V_SUP will be securely observed.
TH8062 – Datasheet
3901008062
Page 17 of 38
March 2006
Rev 002