MG74PG1A08 Datasheet, PDF (80/127 Pages) Megawin Technology Co., Ltd – Interrupt controller

16.2. Serial Port 0 Mode 1
10 bits are transmitted through TXD0, or received through RXD0: a start bit (0), 8 data bits (LSB first), and a stop bit
(1). On receive, the stop bit goes into RB80 in S0CON. The baud rate is determined by the Timer 1 overflow rate.
Figure 16–1 shows the data frame in Mode 1 and Figure 16–6 shows a simplified functional diagram of the serial
port in Mode 1.
Transmission is initiated by any instruction that uses S0BUF as a destination register. The “write to S0BUF” signal
requests the UART0 engine to start the transmission. After receiving a transmission request, the UART0 engine
would start the transmission at the raising edge of TX Clock. The data in the S0BUF would be serial output on the
TXD0 pin with the data frame as shown in Figure 16–1 and data width depend on TX Clock. After the end of 8th data
transmission, TI0 would be asserted by hardware to indicate the end of data transmission.
Reception is initiated when Serial Port 0 Controller detected 1-to-0 transition at RXD0 sampled by RCK. The data on
the RXD0 pin would be sampled by Bit Detector in Serial Port 0 Controller. After the end of STOP-bit reception, RI0
would be asserted by hardware to indicate the end of data reception and load STOP-bit into RB80 in S0CON
register.
Figure 16–6. Serial Port 0 Mode 1, 2, 3
Mode 2
clock source
SYSCLK/2
Mode 1, 3
clock source
Timer 1
Overflow
2
“0” “1”
2
“0” “1”
SMOD1
80C51 Internal BUS
Write
S0BUF
SM00
SM10
TB80
TXBUF
RXBUF
TxD0
RxD0
1
0
SM10
1 RCK
0
SM10
TX Clock
16
UART engine
RI0
TI0
BTI
RX Clock
16
Read
S0BUF
UTIE
STOP-Bit
0
1
9th-Bit
SM00
80C51 Internal BUS
Serial Port 0
Interrupt
ESF
RB80
System Flag
Interrupt
80
MG74PG1A08 Data Sheet
MEGAWIN