MG74PG1A08 Datasheet, PDF (14/127 Pages) Megawin Technology Co., Ltd – Interrupt controller

4.3. Alternate Function Redirection
Many I/O pins, in addition to their normal I/O function, also serve the alternate function for internal peripherals. For
the peripherals UART0, STWI detection, nINT0 and nINT1, Port 1 and Port 3 serve the alternate function in the
default state. However, the user may select other Port to serve their alternate function by setting the corresponding
control bits INT1IS1, INT1IS0 and INT0IS0 in AUXR1 register. P1F1~P1FS0 in AUXR0 register select the
S0/PCA/Timer0/Timer1 function swapped to Port 1. It is especially useful by software programming.
AUXR0: Auxiliary Register 0
SFR Attribute = Normal Read/Write
SFR Address = 0xA1
7
6
5
P17OC1 P17OC0
GF
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
T0XL
P1FS1 P1FS0
R/W
R/W
R/W
1
INT1H
R/W
0
INT0H
R/W
Bit 7~6: P1.7 function configured control bit 1 and 0. The two bits only act when internal RC oscillator (IHRCO or
ILRCO) is selected for system clock source. In external clock input mode, P1.7 is the dedicated clock input pin. In
internal oscillator condition, P1.7 provides the following selections for GPIO or clock source generator. When
P17OC[1:0] index to non-P1.7 GPIO function, P1.7 will drive the on-chip RC oscillator output to provide the clock
source for other devices.
P17OC[1:0]
00
01
10
11
P1.7 function
P1.7
MCK
MCK/2
MCK/4
I/O mode
By P1M0.7 & P1M1.7
By P1M0.7 & P1M1.7
By P1M0.7 & P1M1.7
By P1M0.7 & P1M1.7
Please refer Section “8 System Clock” to get the more detailed clock information. For clock-out on P1.7 function, it is
recommended to set P1M0.7 and P1M1.7 to “11” which selects P1.7 as push-pull output mode.
Bit 2: P1FS1~0, P1.1 and P1.0 alternated function selection.
P1FS[1:0]
P1.1
P1.0
00
Reserved
Reserved
01
TXD0
RXD0
10
PWM0S
CEX0
11
T1/T1CKO
T0/T0CKO
AUXR1: Auxiliary Control Register 1
SFR Attribute = Normal Read/Write
SFR Address = 0xA2
RESET = 0000-0000
7
6
5
4
3
2
1
0
INT1IS1 INT1IS0 INT0IS0
GF
STAF
STOF PTCKOE
GF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7~6: INT1IS1~0, input selection bits of nINT1, TWI_SCL and TWI_SDA, which function is defined as following
table.
INT1IS.1~0 nINT1 & TWI_SCL
TWI_SDA
00
P1.0
P1.1
01
P1.4
P1.5
10
P3.0
P3.1
11
P3.7
P3.6
Bit 5: INT0IS0, nINT0 input selection bits which function is defined as following table.
INT0IS.0
0
1
nINT0
P3.2
P1.6
14
MG74PG1A08 Data Sheet
MEGAWIN