MG74PG1A08 Datasheet, PDF (52/127 Pages) Megawin Technology Co., Ltd – Interrupt controller

13.3. Interrupt Enable
Table 13–3. Interrupt enable control
No
Source Name
#1 External Interrupt 0,nINT0
#2 Timer 0
#3 External Interrupt 1,nINT1
#4 Timer 1
#5 Serial Port 0(UART0)
#6 Expanded Interrupt 1
Enable Bit
EX0
ET0
EX1
ET1
ES0
EXPIE1
Bit Location
IE.0
IE.1
IE.2
IE.3
IE.4
IE.5
There are 6 interrupt sources available in MG74PG1A08. Each of these interrupt sources can be individually
enabled or disabled by setting or clearing an interrupt enable bit in the register IE. IE also contains a global disable
bit, EA, which can be cleared to disable all interrupts at once. If EA is set to ‘1’, the interrupts are individually enabled
or disabled by their corresponding enable bits. If EA is cleared to ‘0’, all interrupts are disabled.
13.4. Interrupt Priority
The priority scheme for servicing the interrupts is the same as that for the standard 80C51. The Priority Bits (see
Table 13–1) determine the priority level of each interrupt. IP0L determines to two-level priority interrupt. Table 13–4
shows the bit values and priority levels associated with each combination.
Table 13–4. Interrupt priority level
{ IP0L.x}
Priority Level
1
1 (high)
0
2 (low)
Each interrupt source has one corresponding bit to represent its priority which is located in IP0L register.
Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two interrupt requests of different
priority levels are received simultaneously, the request of higher priority is serviced. If interrupt requests of the same
priority level are received simultaneously, an internal polling sequence determine which request is serviced. Table
13–2 shows the internal polling sequence in the same priority level and the interrupt vector address.
52
MG74PG1A08 Data Sheet
MEGAWIN