MG74PG1A08 Datasheet, PDF (37/127 Pages) Megawin Technology Co., Ltd – Interrupt controller

11.2.7. Interrupt Recovery from Power-down
Two external interrupts may be configured to terminate Power-down mode. External interrupts nINT0 (P3.2/P1.6),
nINT1 (P1.0/P1.4/P3.0/P3.7) may be used to exit Power-down. To wake up by external interrupt nINT0, nINT1, the
interrupt must be enabled and configured for level-sensitive operation. If the enabled external interrupts are
configured to edge-sensitive operation (Falling or Rising), they will be forced to level-sensitive operation (Low level
or High level) by hardware in power-down mode.
When terminating Power-down by an interrupt, the wake up period is internally timed. At the falling edge on the
interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal
clock will not be allowed to propagate and the CPU will not resume execution until after the timer has reached
internal counter full. After the timeout period, the interrupt service routine will begin. To prevent the interrupt from
re-triggering, the ISR should disable the interrupt before returning. The interrupt pin should be held low until the
device has timed out and begun executing.
11.2.8. Reset Recovery from Power-down
If P1.7 is configured for nRST input pin, wakeup from Power-down through an external reset is similar to the
interrupt. At the rising edge of nRST, Power-down is exited, the oscillator is restarted, and an internal timer begins
counting. The internal clock will not be allowed to propagate to the CPU until after the timer has reached internal
counter full. The nRST pin must be held high for longer than the timeout period to ensure that the device is reset
properly. The device will begin executing once nRST is brought low.
It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution,
from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external memory.
11.2.9. KBI wakeup Recovery from Power-down
All of the GPIOs of MG74PG1A08, P1.7 ~ P1.0, P3.7~P3.6 and P3.2~P3.0 have wakeup CPU capability that are
nibble enabled by the control bit in KBIEN0 and the associated port pin is configured to digital input only mode.
Please refer Section “12.1.5 Port 3 Digital-Input-Only (High Impedance Input) Structure” and Section “12.1.11 Port 3
Digital-Input-Only (High Impedance Input) Structure” for the input mode configuration.
Wakeup from Power-down through an enabled KBI GPIO is similar to the interrupt. At the low-level of enabled KBI
GPIO, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will
not be allowed to propagate to the CPU until after the timer has reached internal counter full. After the timeout period,
CPU will meet a KBI interrupt and execute the interrupt service routine. Please refer Section “17 Keypad Interrupt
(KBI)” for more detail information.
11.2.10. USB wakeup Recovery from Power-down
If USB function is enabled and USB host is connected to MG74PG1A08, USB host reset and resume event will
wake up CPU from power down mode. Wakeup from Power-down through enabled USB function (DCON0.5) and
enabled USB interrupt (IEN.2 in USB SFR) is same to the interrupt. At the active USB interrupt, Power-down is
exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will not be allowed to
propagate to the CPU until after the timer has reached internal counter full. After the timeout period, CPU will meet a
KBI interrupt and execute the interrupt service routine.
MEGAWIN
MG74PG1A08 Data Sheet
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