MG74PG1A08 Datasheet, PDF (23/127 Pages) Megawin Technology Co., Ltd – Interrupt controller

8. System Clock
There are three clock sources for the system clock: Internal High-frequency RC Oscillator (IHRCO), Internal
Low-frequency RC Oscillator (ILRCO) and External Clock Input. Figure 8–1 shows the structure of the system clock
in MG74PG1A08.
The MG74PG1A08 always boots from IHRCO on 12MHz with divided 2 on system clock. CPU clock divider is
cascaded after system clock with default divided by 4. Software can select the one of the three clock sources by
application required and switches them on the fly. But software needs to settle the clock source stably before clock
switching. In external clock input mode (ECKI), the clock source comes from P1.7 input.
The built-in IHRCO provides the high precision frequency at 12MHz for system clock source. It is the default clock
source in MG74PG1A08 after power-on. To find the detailed IHRCO performance, please refer Section “23.5
IHRCO Characteristics”). In IHRCO mode, P1.7 can be configured to internal MCK output or MCK/2 and MCK/4 for
system application.
The MG74PG1A08 device includes a Clock Multiplier to generate the high speed clock for system clock source. It
generates 4/5.33/8 times frequency of CKM, CKM is shown in Figure 8–1 and its typical input is 6MHz. This function
provides the high speed operation on MCU without external high-frequency clock input. To find the detailed CKM
performance, please refer Section “23.7 CKM Characteristics”).
The built-in ILRCO provides the low power and low speed frequency about 64KHz to WDT and system clock source.
MCU can select the ILRCO to system clock source by software for low power operation. To find the detailed ILRCO
performance, please refer Section “23.6 ILRCO Characteristics”). In ILRCO mode, P1.7 can be configured to
internal MCK output or MCK/2 and MCK/4 for system application.
The system clock, SYSCLK, is obtained from one of these four clock sources through the clock divider, as shown in
Figure 8–1. The user can program the divider control bits SCKS2~SCKS0 (in CKCON0 register) to get the desired
system clock. The default system clock divider is set to “/2” in MG74PG1A08 after power on or reset.
The CPU clock, CPUCLK, divide from system clock. The CPU clock divider, CCKS.1~CCKS.0 default is set to “/4” in
MG74PG1A08 after power on or reset.
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MG74PG1A08 Data Sheet
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