MG74PG1A08 Datasheet, PDF (16/127 Pages) Megawin Technology Co., Ltd – Interrupt controller

DPH: Data Pointer High
SFR Attribute = Normal Read/Write
SFR Address = 0x83
7
6
5
DPH.7
DPH.6
DPH.5
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
DPH.4
DPH.3
DPH.2
R/W
R/W
R/W
1
DPH.1
R/W
0
DPH.0
R/W
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash
memory.
ACC: Accumulator
SFR Attribute = Normal Read/Write
SFR Address = 0xE0
7
6
5
ACC.7
ACC.6
ACC.5
R/W
R/W
R/W
RESET = 0000-0000
4
3
2
ACC.4
ACC.3
ACC.2
R/W
R/W
R/W
This register is the accumulator for arithmetic operations.
1
ACC.1
R/W
0
ACC.0
R/W
B: B Register
SFR Attribute = Normal Read/Write
SFR Address = 0xF0
RESET = 0000-0000
7
6
5
4
3
2
1
0
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register serves as a second accumulator for certain arithmetic operations.
5.2. CPU Timing
The MG74PG1A08 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that
has an 8051 compatible instruction set, and executes instructions in 1~6 clock cycles (about 6~7 times the rate of a
standard 8051 device). It employs a pipelined architecture that greatly increases its instruction throughput over the
standard 8051 architecture. The instruction timing is different than that of the standard 8051.
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles
varying from 2 to 12 clock cycles in length. However, the 1T-80C51 implementation is based solely on clock cycle
timing. All instruction timings are specified in terms of clock cycles. For more detailed information about the
1T-80C51 instructions, please refer Section “24 Instruction Set” which includes the mnemonic, number of bytes, and
number of clock cycles for each instruction.
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MG74PG1A08 Data Sheet
MEGAWIN