MG74PG1A08 Datasheet, PDF (32/127 Pages) Megawin Technology Co., Ltd – Interrupt controller

10.5. Brown-Out Reset
In MG74PG1A08, there are one Power on reset (POR) and two Brown-Out Detectors (BOD0 & BOD1) to monitor
VDD power. POR detects the VDD level by software selecting 1.95V or 2.3V. BOD0 detects the VDD level by
software selecting 2.1V or 2.6V. BOD1 services the fixed detection level at VDD=3.6V. If VDD power drops below
POR, BOD0 or BOD1 monitor level. Associated flag, BOF0 and BOF1, is set. If BO0RE (PCON2.2) is enabled,
BOF0 indicates a BOD0 Reset occurred. If BO1RE (PCON2.3) is enabled, BOF1 indicates a BOD1 Reset occurred.
PCON2: Power Control Register 2
SFR Attribute = Normal Read and Protected Write
SFR Address = 0xBA
POR/RESET = 0100-0000
7
6
5
4
3
2
1
AWBOD1 EBOD1
--
--
BO1RE BO0RE
--
R/W
R/W
W
W
R/W
R/W
W
0
RMLS
R/W
Bit 7: AWBOD1, Awaked BOD1 in PD mode.
0: BOD1 is disabled in power-down mode.
1: BOD1 keeps operation in power-down mode.
Bit 6: EBOD1, Enable BOD1 that monitors VDD power dropped below 3.6V.
0: Disable BOD1 to slow down the chip power consumption.
1: Enable BOD1 to monitor VDD power dropped.
Bit 5~4: Reserved. Software must write “0” on these bits when PCON2 is written.
Bit 3: BO1RE, BOD1 Reset Enabled.
0: Disable BOD1 to trigger a system reset when BOF1 is set.
1: Enable BOD1 to trigger a system reset when BOF1 is set.
Bit 2: BO0RE, BOD0 Reset Enabled.
0: Disable BOD0 to trigger a system reset when BOF0 is set.
1: Enable BOD0 to trigger a system reset when BOF0 is set (VDD meets 2.1V or 2.6V).
Bit 1: Reserved. Software must write “0” on these bits when PCON2 is written.
Bit 0: RMLS, Power on Reset (POR) and Brown-Out detector 0(BOD0) monitored level Selection. The initial values
of this bit is loaded from RMLSO.
RMLS
0
1
POR detecting level
1.95V
2.3V
BOD0 detecting level
2.1V
2.6V
PCON1: Power Control Register 1
SFR Attribute = Normal Read/Write or Protected Write
SFR Address = 0x97
POR = 00xx-0000
7
6
5
4
3
SWRF
EXRF
--
--
KBIF
R/W
R/W
W
W
R/W
2
BOF1
R/W
1
BOF0
R/W
0
WDTF
R/W
Bit 2: BOF1, BOF1 (Reset) Flag.
0: This bit must be cleared by software writing “1” on it. Software writing “:0” is no operation.
1: This bit is only set by hardware when VDD meets BOD1 monitored level. Writing “1” on this bit will clear BOF1. If
BO0RE (PCON2.3) is enabled, BOF0 indicates a BOD0 Reset occurred.
Bit 1: BOF0, BOF0 (Reset) Flag.
0: This bit must be cleared by software writing “1” on it. Software writing “:0” is no operation.
1: This bit is only set by hardware when VDD meets BOD0 monitored level. Writing “1” on this bit will clear BOF0. If
BO0RE (PCON2.2) is enabled, BOF0 indicates a BOD0 Reset occurred.
32
MG74PG1A08 Data Sheet
MEGAWIN