97SD3240 Datasheet, PDF(7/39 Page) Maxwell Technologies – 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks

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97SD3240 Datasheet, PDF (7/39 Pages) Maxwell Technologies – 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks

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1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM

Pin Functions:

97SD3240

CLK (INPUT PIN): CLK is the master clock input to this pin. The other input signals are referred at CLK rising

edge.

CS 1-5 (INPUT PINS): When CS 1-5 are low, the command input cycle becomes valid. When CS 1-5 are High,

all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held.

RAS, CAS AND WE (INPUT PINS): Although these pin names are the same as those of conventional DRAMs,

they function in a different way. These pins define operation commands (read, write, etc.) depending on the

combination of their voltage levels.

A0 TO A12 (INPUT PINS): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active

command cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read

or write command cycle CLK rising edge. And this column address becomes burst access start address.

A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are pre-

charged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1

(BS) is pre charged.

BA0/BA1 (INPUT PINS): BA0/BA1 are bank select signals (BS). The memory array of the 97SD3240 is divided

into bank 0, bank 1, bank 2 and bank 3. The 97SD3240 contains 8192-row X 1024-column X 40-bit. If BA0

and BA1 is Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0 is High and

BA1 is Low, bank 2 is selected. If BAO is High and BA1 is High, bank 3 is selected.

CKE 1-5 (INPUT PIN): This pin determines whether or not the next CLK is valid. If CKE 1-5 is High, the next

CLK rising edge is valid. If CKE 1-5 is Low, the next CLK rising edge is invalid. This pin is used for power-

down mode, clock suspend mode and self refresh mode1.

DQM 1-5 (INPUT PINS): DQM 1-5 control input/output buffers

Read operation: If DQM 1-5 are High, the output buffer becomes High-Z. If the DQM 1-5 are Low, the output

buffer becomes Low-Z. ( The latency of DQM 1-5 during reading is 2 clock cycles.)

Write operation: If DQM 1-5 are High, the previous data is held ( the new data is not written). If the DQM 1-5

areLow, the data is written. ( The latency of DQM 1-5 during writing is 0 clock cycles.)

DQ0 TO DQ39 (DQ PINS): Data is input to and output from these pins ( DQ0 to DQ39).

VCC AND VCCQ (POWER SUPPLY PINS): 3.3V is applied. ( VCC is for the internal circuit and VCCQ is for the output

buffer.)

VSS AND VSSQ (POWER SUPPLY PINS): Ground is connected. (VSS is for the internal circuit and VSSQ is for the

output buffer.)

1. Self refresh mode should only be used at temperatures below 70Â°C.

02.04.05 Rev 3

All data sheets are subject to change without notice 7

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