97SD3240 Datasheet, PDF (4/39 Pages) Maxwell Technologies – 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks

1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM
97SD3240
TABLE 4. DC ELECTRICAL CHARACTERISTICS
(V_CC = 3.3V + 0.3V, V_CCQ = 3.3V + 0.3V, T_A = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
TEST CONDITIONS
SUBGROUPS MIN
MAX
UNITS
Standby Current in non power down⁶
Standby Current in non power down⁷
( Input signal stable)
Active standby current in^1,2,4
power down
Active standby current in power down
(input signal stable)^2,5
Active standby power in non power
down^1,2,6
Active standby current in non power
down ( input signal stable)^2,7
Burst Operating Current^1,2,8
CAS Latency = 2
CAS Latency = 3
I_CC2N
I_CC2NS
I_CC3P
I_CC3PS
I_CC3N
I_CC3NS
I_CC4
CKE, CS = V_IH
t_CK = 12 ns
CKE = V_IH
t_CK = 0
CKE = V_IL
t_CK = 12 ns
CKE = V_IL
t_CK = 0
CKE, CS1-6 = V_IH
t_CK = 12 ns
CKE = V_IH
t_CK = 0
t_CK = min
BL = 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
100 mA
45
mA
20
mA
15
mA
150 mA
75
mA
mA
550
725
Refresh Current³
I_CC5
t_RC = min
1, 2, 3
1100 mA
Self Refresh current⁹
I_CC6
V_IH>V_CC - 0.2V
1, 2, 3
V_IL < 0.2 V
15
mA
Input Leakage Current - CLK
I_LI
0<V_LI<V_CC
1, 2, 3
-3
3
uA
Input Leakage Current - All Other
I_LI
0<V_LI<V_CC
1, 2, 3
-5
5
uA
Output Leakage Current
I_LO
0<V_LO<V_CC
1, 2, 3 -1.5
1.5
uA
Output high voltage
V_OH
I_OH = -4mA
1, 2, 3 2.4
V
Output low voltage
V_OL
I_OL = 4 mA
1, 2, 3
0.4
V
1. I_CC1 depends on output load conditions when the device is selected. I_CC1(max) is specified with the output open.
2. One Bank Operation
3. Input signals are changed once per clock.
4. After power down mode, CLK operating current.
5. After power down mode, no CLK operating current.
6. Input signals are changed once per two clocks.
7. Input signals for V_IH or V_IL are fixed.
8. Input signals are changed once per four clocks.
9. After self refresh mode set, self refresh current. Use Self Refresh for temperatures less than 70 °C ONLY.
02.04.05 Rev 3
All data sheets are subject to change without notice 4
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