97SD3240 Datasheet, PDF (25/39 Pages) Maxwell Technologies – 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks

1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM
97SD3240
Write command to Write command interval:
1. Same bank, same ROW address: When another write command is executed at the same ROW address
of the same bank as the preceding write command, the second write can be performed after as interval of no
less than 1 clock. In the case of burst writes, the second write command has priority.
Write to Write Command Interval (Same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two write commands with a precharge command and a
bank-active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second
write command has priority.
WRITE to WRITE Command Interval (Different bank)
02.04.05 Rev 3
All data sheets are subject to change without notice 25
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