97SD3240 Datasheet, PDF(34/39 Page) Maxwell Technologies – 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks

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97SD3240 Datasheet, PDF (34/39 Pages) Maxwell Technologies – 1.25Gb SDRAM 8-Meg X 40-Bit X 4-Banks

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1.25Gb (8-Meg X 40-Bit X 4-Banks) SDRAM

97SD3240

Mode register set to Bank-active interval: The interval between setting the mode register and executing a

bank-active command must be no less than IRSA.

DQM Control

The DQM mask the bytes of the DQ data. The timing of DQM is different during reading and writing.

Reading: When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output

buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z and

the corresponding data is not output. However, internal reading operations continue. The latency of DQM

during reading is 2 clocks.

Writing: Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when

DQM is set to High, the corresponding data is not written, and previous data is held. The latency of DQM

during writing is 0 clock.

Reading

02.04.05 Rev 3

All data sheets are subject to change without notice 34

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