SSC050-01 Datasheet, PDF (9/79 Pages) Maxim Integrated Products – Two-Wire Serial Backplane Controller

Functional Description
Two-wire Serial Interface
Chapter 2 FUNCTIONAL DESCRIPTION
SSC050-01
Data Sheet
The SSC050-01 is composed of five major functional blocks; a slave mode two-wire serial interface, a
block of control registers, general purpose I/O and specialized port bypass control logic, a clock
generator and power-on reset control logic. The SSC050-01 fully supports a generic two-wire serial
interface and is compatible with other industry standard devices which also support this interface at both
100K and 400K bits per second.
TWO-WIRE SERIAL INTERFACE
The device supports a single slave mode two-wire serial interface. All inter-chip communication to a
microcontroller takes place over this bus. The interface supports a three-bit address bus, which allows
the user to select one of eight possible addresses. The address bus is compared to bits three through one
of the slave address byte, which is the first byte transmitted to the device after a start condition. The
SSC050-01 supports two pin selectable four-bit device type identifier values, 1000b and 1100b. The
address bits and the device identifier allow the use of up to 16 devices on a single two-wire serial
interface. The serial interface control logic includes the slave state machine, address comparison logic,
serial to parallel and parallel to serial conversion, register read/write control and filtering for the clock
and data line.
A read or write transaction is determined by the least significant bit (R/W) of the first byte transferred.
Write accesses require a three-byte transfer. The first byte is the slave address with the R/W bit low, the
second byte contains the register address and the third byte is the write data. Read accesses require a
four-byte transfer since data transfer direction can not change after receipt of the slave address byte. The
first byte is the slave address with the R/W bit low, the second byte contains the register address, the
third byte is a repeated slave address with the R/W bit high and the fourth byte is the read data. If the
transaction is a write, the data will be latched into the appropriate register during the acknowledge of the
third byte. All transactions to or from the device complete during the acknowledge of the third byte
allowing the user to immediately initiate another transfer to the device. Sequential read or write
transactions are allowed and are extensions of the above protocol with additional data bytes added to the
end of the transaction. All sequential transactions will cause the internal address to increment by one
regardless of the register address.
2-1
Revision 4.0
November 10, 2004