SSC050-01 Datasheet, PDF (44/79 Pages) Maxim Integrated Products – Two-Wire Serial Backplane Controller

Control Registers
Control Register Definition
SSC050-01
Data Sheet
38h: Fan Speed Control 2 (FSC2)
Register Name:
Address:
Reset Value:
Description
FSC2
38h
00XX_XX00b
Fan Speed Control 2.
This register affects pin P2.6
7
6
5
4
3
Fan Speed
Control Ena-
ble
Fan Speed
Interrupt Ena-
ble
2
1
0
Fan Divisor 1 Fan Divisor 0
Bit(s) Bit Label
7 FSCEN
6 FSIEN
1:0 FD1-0
Access Description
R/W Fan Speed Control Enable
When this bit is set, P2.6 is automatically configured to provide a fan speed monitor-
ing input. Configurations for this I/O pin which may have previously been enabled
through other control registers will be overridden except for the bypass select func-
tion (bits 6 and 5 of the appropriate Bit Control Registers). If the appropriate bypass
bits have been set, the odd numbered fan speed input pins (P1.1, P1.3, P1.5, P1.7,
P2.1, P2.3, P2.5 or P2.7) will be configured as outputs. When this bit is reset, the
remaining bits in this register have no effect on the operation of P2.6.
When enabled as a fan speed monitoring input, pulses from the fan tachometer out-
put gate an internal 20KHz clock into an eight-bit counter. A divisor value stored in
bits one and zero of this register allow the user to select one of four nominal RPM
values based on fan tachometer outputs which pulse twice per revolution. The
FSCC2 register provides the user with an accurate binary fan speed count value
which can be used to determine the current RPM value of the fan. Incoming pulses
are filtered and conditioned to accommodate the slow rise and fall times typical of
fan tachometer outputs. The maximum input signal is limited to a range of VSS to
VDD. If this input is supplied from a fan tachometer output which exceeds this range,
external components will be required to limit the signal to an acceptable range.
R/W Fan Speed Interrupt Enable
When this bit is set, the P2.6 input will be enabled to generate an interrupt if the
eight bit counter value is greater than or equal to the count overflow value loaded
into the FSCO0 register. If the condition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, the fan speed monitoring logic will not generate an interrupt condition.
R/W Fan Divisor
These two bits determine the divisor value used to determine the correct range of
RPM values supplied to the eight-bit fan speed counter. Table 4-5 describes the
available divisor values:
The decimal count value can be calculated using the following equation:
Decimal-Count-Value = (1,200,000)/(RPM X Divisor)
Any nominal RPM value can be used in the above equation along with the appropri-
ate divisor as long as the maximum non-failure count value does not exceed the lim-
its of an eight-bit counter. Typical applications may consider 60% to 70% of normal
RPM a fan failure which would result in a decimal count value of 250 (FAh) and 214
(D6h) respectively at the above stated RPM values.
Revision 4.0
November 10, 2004
4-28