SSC050-01 Datasheet, PDF (33/79 Pages) Maxim Integrated Products – Two-Wire Serial Backplane Controller

Control Registers
Control Register Definition
SSC050-01
Data Sheet
25h: Port Bypass Control 5 (PBC5)
Register Name:
Address:
Reset Value:
Description
PBC5
25h
00XX_XX1Xb
Port Bypass Control 5
7
6
5
4
3
Port Bypass
Control Ena-
ble
Signal
Detected
Interrupt Ena-
ble
2
1
0
Force
Bypass
Signal
Detected
Bit(s) Bit Label
7 PBCEN
6 SDIEN
1 FB
0 SD
Access Description
R/W Port Bypass Control Enable
When this bit is set, P4.3 and P4.2 are automatically configured to provide a Force
Bypass output pin and a Signal Detected input pin. Configurations for these I/O pins
which may have previously been enabled through other control registers will be
overridden except for the bypass select function (bits 6 and 5 of the appropriate Bit
Control Registers). When this bit is reset, the remaining bits in this register have no
effect on the operation of P4.3 and P4.2.
R/W Signal Detected Interrupt Enable
When this bit is set, the SD input will be enabled to generate an interrupt if a transi-
tion occurs on the pin. If a transition occurs, the INT# pin will assert and a binary
value equal to the address of this register will appear in the BCIS register. When this
bit is reset, transitions on the signal detected input will not generate an interrupt con-
dition.
R/W Force Bypass
This bit controls the P4.3 I/O pin, which is configured as a totem pole output by set-
ting the PBCEN bit. When this bit is set, the force bypass input of a PBC/CRU/SDU
function is not enabled and the port bypass circuit is in normal mode. When this bit is
reset, the force bypass function of a PBC/CRU/SDU function is enabled and the port
bypass circuit is in bypass mode. This register bit is automatically cleared when the
synchronized and filtered P4.2 input is low which results in a maximum latency of
400 nanosceonds from detection of the loss of a high speed signal to the de-asser-
tion of the P3.1 output.
NOTE: Since all I/O pins on the device power-on as inputs with weak internal pull-ups, it
is possible to define the default state of the force bypass function through the use
of an external pull-down resistor. The default state of the I/O can be determined
by reading this register since the read value of the register bits are always avail-
able through an input synchronizer and filter. Once the default state is deter-
mined, a write to the FB bit of this register with the default values as well as
setting the PBCEN bit ensures that the port bypass control functions have been
enabled correctly. Additional writes to this register can enable or disable the
force bypass functions at any time as long as the SD input remains high.
R/W Signal Detected
When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O
pin which has been connected to the signal detected output of a PBC/CRU/SDU
function. If this bit is set, a high speed signal has been detected by the signal detect
unit. If this bit is reset, a high speed signal has not been detected by the signal
detect unit.
Revision 4.0
November 10, 2004
4-17