SSC050-01 Datasheet, PDF (10/79 Pages) Maxim Integrated Products – Two-Wire Serial Backplane Controller

Functional Description
Control Registers
SSC050-01
Data Sheet
CONTROL REGISTERS
The SSC050-01 contains five groups of control registers. Each group supports a specific function within
the device as follows; the first group is the port data registers, the second is the data direction registers,
the third contains special bit control features, the fourth supports the port bypass control function and
the fifth supports fan speed monitoring. Currently the device contains 78 registers to support all required
functions. In normal I/O operation, each eight-bit group of I/O pins are controlled by a pair of registers,
Port Data and Data Direction. The use of these pairs of registers allows each I/O line to be individually
configured as an input with internal pull-up, output or open drain output with internal pull-up.
The bit control features are enabled through a separate register for each I/O pin. The Bit Control
registers allow the user to independently configure each I/O pin to enable one of the special control
features as well as control Port Data and Data Direction (which are shadowed copies of the standard
control bits found in the Port Data and Data Direction registers). Each I/O pin which has been
configured as an input can also be configured to assert the open drain interrupt pin when a rising edge, a
falling edge or either edge is detected on the I/O pin. An Interrupt Status register provides the user with
a binary indication of which I/O pin is the source of the current interrupt. Each I/O pin which is
configured as an output can automatically generate one of seven selectable flashing rates, which are
normally driven in an open drain mode. By providing all I/O control capability in a single register, the
user can control the operation of the I/O on a pin-by-pin basis.
The Port Bypass registers control the operation of a selected group of I/O lines which can be dedicated
to support various combinations of individual PBC/CRU/SDU functions as well as integrated solutions.
Enabling port bypass control causes the normal or bit control register settings to be overridden and any
further changes to the affected registers will have no effect. Each Port Bypass Control register will
automatically configure the I/O lines to support a Force Bypass output and a Signal Detected input.
The Fan Speed registers control the operation of four programmable inputs which can be used to
monitor signals from fans equipped with tachometer outputs. Enabling fan speed control causes the
normal or bit control register settings to be overridden and any further changes to the affected registers
will have no effect. Each group of three registers provides the capability to enable the function, establish
a user defined RPM overflow value which indicates a failure and determine the current RPM value of
the fan. The digital filters on the fan speed inputs can optionally be enabled to increase the normal 100
to 200 nanosecond filter to 400 to 500 nanoseconds.
The Pulse Width Modulation Control registers enable internal logic to provide duty cycles of 0% to
100% in 3% increments at default frequencies of 26KHz, 52KHz and 104KHz. Optionally, the PWM
outputs can be programmed for three additional frequency ranges of 5.2KHz, 10.4KHz and 20.8KHz or
1.04KHz, 2.08KHz and 4.16KHz or 208Hz, 416Hz and 833Hz. These outputs can vary the speed of up
to four fans through the use of external drivers and power MOSFETs or pulse width to voltage
converters. They can also be used to support other pulse width modulated requirements within the
system.
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Revision 4.0
November 10, 2004