SSC050-01 Datasheet, PDF (11/79 Pages) Maxim Integrated Products – Two-Wire Serial Backplane Controller

Functional Description
I/O Logic
SSC050-01
Data Sheet
I/O LOGIC
Each general purpose I/O pin is controlled by a set of registers in the Control Register Block. The I/O
supports a high current drive output buffer, which can be configured as a totem pole or open drain driver.
The input section of the I/O supports TTL signaling and includes an internal weak pull-up device. This
allows unused I/O pins to be left unconnected without high current drain issues. The port bypass control
I/O pins which are shared with Port 3 and Port 4 are generated using the same buffer logic as the other
ports. When enabled in port bypass control mode, internal logic overrides the existing configuration,
with each I/O pin dedicated to the specific port bypass function. All I/O lines default as inputs with the
weak internal pull-up enabled.
CLOCK GENERATOR
Clock generation for the device is composed of an internal oscillator, divider circuits and a distribution
network. The primary clock frequency of 10.0MHz is used for filtering incoming serial interface signals
and interrupt sources as well as clocking the slave state machine. Divided clocks provide the source for
LED flash rate generators. Logic within the SSC050-01 synchronizes the divided clocks between
devices attached to the same two-wire serial bus with no more than 200 nanoseconds of skew. Multiple
devices can then be used to drive different LED's at the same frequency, providing a synchronized
visible indication. The oscillator provides a stable clock source for the device and requires the use of an
off chip crystal and related passive components or external clock source. There are no programmable
options related to clock generation except the selection of the seven fixed LED Flashing rates. The
SSC050-01 can operate at frequencies other than 10.0MHz and continue to meet both the standard mode
(100KHz) and fast mode (400KHz) serial interface timings. Frequencies from 8.0MHz to 12.5MHz are
allowable as long as they meet the AC timing requirements listed in section 5.3.1 of this manual.
Operation of the LED flashing circuits, fan speed counters and pulse width modulated outputs will be
affected by a change in base operating frequency. The user must scale the expected operating parameters
by the change in frequency from a nominal 10.0MHz. As and example, operating the SSC050-01 at
8.0MHz will cause the LED flashing circuits, fan speed counters and pulse width modulated outputs to
operate 25% slower than normal.
POWER-ON RESET
Power-On Reset is accomplished by the use of logic internal to the device. No external components are
required. After power-on, the serial interface state machine will always return an idle state waiting for a
start condition to appear on the SCL and SDA pins. A proper power-on reset sequence will clear the
serial interface state machine, the clock generators, the control registers, the I/O control logic and the
port bypass control logic. The divided clocks used for LED flash rate generation will also be in a known
state. An external reset circuit utilizing the TEST1 and ASEL pins can be developed as an option to the
internal Power-On Reset logic. Regardless of the effectiveness of either power-on reset sequence, it is
highly recommended that the control registers and I/O control logic be cleared through the Soft Reset
Register bit. This can be accomplished by writing a 80h to the BCT Register (FCh) followed
immediately by a STOP condition. This bit is self resetting and will not require further attention.
2-3
Revision 4.0
November 10, 2004